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r1ex24002asas0a r1ex24002atas0a two-wire serial interface 2k eeprom (256-word 8-bit) rej03c0354-0101 rev.1.01 jan. 9, 2009 description r1ex24xxx series are two-wire serial interface eep rom (electrically erasable and programmable ro m). th ey realize h i g h sp eed , lo w p o w er co n s u m p t io n an d a h i g h lev e l o f reliab ility b y emp l o y i n g advanced m nos memory t echnol ogy and c m os proce ss and l o w vol t a ge ci rcui t r y t echnol ogy. they al so have a 16-byt e page programmi ng funct i on t o make t h ei r wri t e operat i on fast er. not e : r e nesas technol ogy?s seri al eepr o m are aut hori zed for usi ng consumer appl i cat i ons such as cel l u l a r phone, camcorders, audi o equi pment . therefore, pl ease cont act r e nesas technol ogy?s sal e s offi ce before usi ng i ndust r i a l appl i cat i ons su ch as aut o mot i ve syst ems, embedded cont rol l ers, and met e rs. features ? si ngl e suppl y: 1.8 v t o 5.5 v ? two-wire serial interface (i 2 c serial bus) ? c l ock frequency: 400 khz ? power di ssi pat i on: ? st andby: 2 a (max) ? active (read): 1 ma (max) ? active (write): 2.5 ma (max) ? aut o mat i c page wri t e : 16-byt e/ page ? write cycle time: 5 ms ? endurance: 1,000k c y cl es @25 c ? dat a ret e nt i on: 100 years @25 c rej03c0354-0101 rev. 1.01 jan.9, 2009 page 1 of 22
r1ex24002axxs0a ? small size packages: sop-8pin, tssop-8pin ? shi ppi ng t a pe and reel ? tssop 8-pi n: 3,000 ic / r eel ? sop 8-pi n: 2,500 ic / r eel ? temperature range: ? 40 t o +85 c ? lead free product s . ordering information type no. internal organization operating voltage f requency package r 1 e x 2 4 0 0 2 a s a s 0 a 2 k b i t (256 8-bit) 1.8 v to 5.5 v 400 khz 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free r 1 e x 2 4 0 0 2 a t a s 0 a 2 k b i t (256 8-bit) 1.8 v to 5.5 v 400 khz 8-pin plastic tssop ptsp0008jc-b (ttp-8dav) lead free pin arrangement /8-pin tssop 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sda (top view) 8-pin sop rej03c0354-0101 rev.1.01 jan. 9, 2009 page 2 of 22
r1ex24002axxs0a pin description pin name function a0 to a2 device address scl serial clock input sda serial data input/output w p w r i t e p r o t e c t v cc p o w e r s u p p l y v ss g r o u n d n c n o c o n n e c t i o n block diagram control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp a0, a1, a2 scl sda absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss v i n ? 0.5 * 2 to +7.0 * 3 v operating temperature range * 1 t o p r ? 40 to + 85 c storage temperature range tstg ? 55 to + 125 c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width 50 ns. 3. should not exceed v cc + 1.0 v. rej03c0354-0101 rev.1.01 jan. 9, 2009 page 3 of 22
r1ex24002axxs0a dc operating conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t supply voltage v cc 1 . 8 ? 5 . 5 v v ss 0 0 0 v input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il ? 0.3 * 1 ? v cc 0.3 v operating tem p e r a t u r e t o p r ? 40 ? + 8 5 c notes: 1. v il (min): ? 1.0 v for pulse width 50 ns. dc characteristics (ta = ? 40 t o +85 c, v cc = 1.8 v t o 5.5 v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t t e s t c o n d i t i o n s input leakage current i li ? ? 2 . 0 a v cc = 5.5 v, vin = 0 to 5.5 v output leakage current i lo ? ? 2 . 0 a v cc = 5.5 v, vout = 0 to 5.5 v standby v cc current i sb ? 1 . 0 2 . 0 a vin = v ss or v cc read v cc current i cc1 ? ? 1 . 0 m a v cc = 5.5 v, read at 400 khz write v cc current i cc2 ? ? 2 . 5 m a v cc = 5.5 v, w r ite at 400 khz output low voltage v ol 2 ? ? 0 . 4 v v cc = 2.7 to 5.5 v, i ol = 3.0 ma v ol 1 ? ? 0 . 2 v v cc = 1.8 to 2.7 v, i ol = 1.5 ma capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (a0 to a2, scl, w p ) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (sda) c i/o * 1 ? ? 6.0 pf vout = 0 v notes: 1. not 100 % tested. memory cell characteristics (v cc = 1.8 v t o 5.5 v) t a = 2 5 c t a = 8 5 c n o t e s endurance 1,000k cycles min. 100k cycles min 1 data retention 100 years min. 10 years min. 1 note: 1. not 100 % tested rej03c0354-0101 rev.1.01 jan. 9, 2009 page 4 of 22
r1ex24002axxs0a ac characteristics (ta = ? 40 t o +85 c, v cc = 1.8 t o 5.5 v) test conditions ? input pul es l e vel s : ? v il = 0.2 v cc ? v ih = 0.8 v cc ? input ri se and fal l t i me: 20 ns ? input and out put t i m i ng reference l e vel s : 0.5 v cc ? output load: ttl gate + 100 pf p a r a m e t e r s y m b o l m i n t y p m a x u n i t n o t e s clock frequency f scl ? ? 4 0 0 k h z clock pulse width low t lo w 1 2 0 0 ? ? n s clock pulse width high t high 6 0 0 ? ? n s noise suppression time t i ? ? 5 0 n s 1 access time t aa 1 0 0 ? 9 0 0 n s bus free time for next mode t buf 1 2 0 0 ? ? n s start hold time t hd.sta 6 0 0 ? ? n s start setup time t su.sta 6 0 0 ? ? n s data in hold time t hd.dat 0 ? ? n s data in setup time t su.dat 1 0 0 ? ? n s input rise time t r ? ? 3 0 0 n s 1 input fall time t f ? ? 3 0 0 n s 1 stop setup time t su.sto 6 0 0 ? ? n s data out hold time t dh 5 0 ? ? n s w r ite protect hold time t hd.wp 1 2 0 0 ? ? n s w r ite protect setup time t su.wp 0 ? ? n s write cycle time t wc ? ? 5 m s 2 notes: 1. not 100 % tested. 2. t wc is the time from a stop condition to t he end of internally controlled write cycle. rej03c0354-0101 rev.1.01 jan. 9, 2009 page 5 of 22
r1ex24002axxs0a timing waveforms bus timing t f 1/f scl t high t su .st a t hd .st a t hd .d a t t su .d a t t su .st o t bu f t dh t aa t lo w t r scl wp sd a (in) sd a (out) t su .wp t hd .wp scl sd a d0 in wr ite data a c k (address (n)) t wc (inter nally controlled) stop condition star t condition write cycle timing rej03c0354-0101 rev.1.01 jan. 9, 2009 page 6 of 22
r1ex24002axxs0a pin function seri al cl ock (scl) the sc l pi n i s used t o cont rol seri al i nput / out put dat a t i m i ng. the sc l i nput i s used t o posi t i ve edge clock data into eeprom device and ne gative edge clock data out of each device. maximum clock rate is 400 khz. serial input/output data (sda) the sda pi n i s bi di rect i onal for seri al dat a t r ansfer. the sda pi n needs t o be pul l e d up by resi st or as t h at pi n i s open-drai n dri v en st ruct ure. use proper resi st or val u e for your syst em by consi d eri ng v ol , i ol and t h e sda pi n capaci t a nce. except for a st art condi t i on and a st op condi t i on whi c h wi l l be di scussed l a t e r, t h e sda t r ansi t i on needs t o be compl e t e d duri ng t h e sc l l o w peri od. d a ta v a lidity (sda dat a change t i m i ng waveform) scl sd a data change data change note: high-to-low and low-to-high change of sda should be done during the scl low period. rej03c0354-0101 rev.1.01 jan. 9, 2009 page 7 of 22
r1ex24002axxs0a device address (a0, a1, a2) ei ght devi ces can be wi red for one common dat a bus l i ne as maxi mum. devi ce address pi ns are used t o distinguish each device a nd device address pins s hould be connected to v cc or v ss . when devi ce address code provi ded from sda pi n mat c hes correspondi ng hard-wi r ed devi ce address pi ns a0 t o a2, t h at one device can be activated. pin connections for a0 to a2 p i n c o n n e c t i o n memory size max connect number a2 a1 a0 note 2k bit 8 v cc /v ss v cc /v ss v cc /v ss note: 1. during floating, ?v cc /v ss ? are fixed to v ss . write protect (wp) when t h e wri t e prot ect pi n (wp) i s hi gh, t h e wri t e prot ect i on feat ure i s enabl e d and operat e s as shown i n th e fo llo w i n g tab l e. also, acknowledgment "0" is outputted after inpu tting device address and me mory address. after i nput t i ng wri t e dat a , acknowl e dgment "1"" (no ack) i s out put t e d. wh en th e wp is lo w , w r ite o p e ratio n fo r all memo ry arrays are allowed. the read operation is always activated irrespective of the wp pin status. write protect area w r ite protect area wp pin status 2k bit v ih full (2k bit) v il normal read/write operation rej03c0354-0101 rev.1.01 jan. 9, 2009 page 8 of 22
r1ex24002axxs0a functional description start condition a hi gh-t o -l ow t r ansi t i on of t h e sda wi t h t h e sc l hi gh i s needed i n order t o st art read, wri t e operat i on (see st art condi t i on and st op condi t i on). stop condition a l o w-t o -hi gh t r ansi t i on of t h e sda wi t h t h e sc l hi gh i s a st op condi t i on. the st and-by operat i on st art s aft e r a read sequence by a st op condi t i on. in t h e case of wri t e operat i on, a st op condi t i on t e rmi n at es t h e write data inputs and place the device in a internally -timed write cycle to th e memories. after the in tern ally -timed w r ite cy cl e which is specified as t wc , t h e devi ce ent e rs a st andby mode (see wri t e cycl e timin g ) . start condition and stop condition scl sd a (in) stop condition star t condition rej03c0354-0101 rev.1.01 jan. 9, 2009 page 9 of 22
r1ex24002axxs0a acknowl edge all addresses and data words are serially transmitted to and from in 8-bit words. the receiver sends a zero to acknowledge that it has received each word. this happens during ni nth clock cycle. the transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. in the write operation, eeprom sends a zero to acknowledge after recei ving every 8-bit words. in the read operation, eeprom sends a zero to acknowledge after receiving th e device address word. after sending read data, the eeprom waits acknowledgment by keeping bus open. if the eeprom receives zero as an acknowledge, it sends read data of next addre ss. if the eeprom receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operati on and enters a stand-by mode. if the eeprom receives neither acknowledgment "0" nor a stop condition, the eeprom keeps bus open wi t hout sendi ng read dat a . acknowledge timing waveform scl sd a in sd a out 12 8 9 ac kno wledge out rej03c0354-0101 rev.1.01 jan. 9, 2009 page 10 of 22
r1ex24002axxs0a device addressing the eepr o m devi ce requi res an 8-bi t devi ce address word fol l owi ng a st art condi t i on t o enabl e t h e chi p for a read or a wri t e operat i on. the devi ce addre ss word consi s t s of 4-bi t devi ce code, 3-bi t devi ce address code and 1-bi t read/ w ri t e (r / w ) code. the most si gni fi cant 4-bi t of t h e devi ce address word are used t o di st i ngui sh devi ce t ype and t h i s eepr o m us es ?1010? fi xed code. the devi ce address word i s fol l owed by t h e 3-bi t devi ce address code a2, a1,a0 . the devi ce address code sel ect s one devi ce out of ei ght devi ces whi c h are connect ed t o t h e bus. thi s means t h at t h e devi ce i s sel ect ed i f t h e i nput t e d 3-bi t devi ce address code i s equal t o t h e correspondi ng hard-wi r ed a2 t o a0 pi ns st at us. the ei ght h bi t of t h e d e v i ce ad d r ess w o rd is th e read /w rite(r/w) b it. a w r ite operation is initiated if this bit is ?0? and a read o p e ratio n is in itiated if th is b it is ?1 ? . th e eepro m tu rn s to a stan d - b y state if th e d e v i ce co d e is n o t ?1010? or devi ce address code doesn?t coi n ci de wi t h st at us of t h e correspond hard-wi r ed devi ce address pi ns. device address word device address word (8-bit) device code (fixed) device address code r/w code * 1 2 k 1 0 1 0 a 2 a 1 a 0 r/w note: 1. r/w = ? 1? is read and r/w = ?0? is write. rej03c0354-0101 rev.1.01 jan. 9, 2009 page 11 of 22
r1ex24002axxs0a write operations (wp =low ) byte write: (write operation during wp =low st at us ) a wri t e operat i on requi res an 8-bi t devi ce address word wi t h r / w = ?0?. then t h e eepr o m sends acknowledgment "0" at the ninth clock cycle. afte r these, the 2k bit eeprom receives 8-bit memory address words. upon receipt of this memory address, the eeprom outputs acknowledgment "0" and receives a following 8-bit write data. after recei pt of write data, the eeprom outputs acknowledgment "0". if the eeprom receives a stop condition, the eep rom enters an internally -timed write cycle and terminates receipt of scl, sda i nputs until completion of the write cycle. the eeprom returns to a st andby mode aft e r compl e t i on of t h e wri t e cycl e. byte write operation de vice address memor y address wr ite data (n) 2k 10 10 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k r/w ac k wp rej03c0354-0101 rev.1.01 jan. 9, 2009 page 12 of 22
r1ex24002axxs0a page wri t e: the eepr o m i s capabl e of t h e page wri t e operat i on wh i c h al l o ws any number of byt es up t o 16 byt es t o be written in a single write cycle. the page write is the same sequence as the byte write except for i nput t i ng t h e more wri t e dat a . the page wri t e i s i n i t i at ed by a st art condi t i on, devi ce address word, memory address(n) and wri t e dat a (dn) wi t h every ni nt h bi t acknowl e dgment . the eepr o m ent e rs t h e page write operation if the eeprom receives more write data (dn+1) inst ead of receiving a stop condition. the a0 to a3 address bits are automatically incremented upon receiving write data (dn+1). the eeprom can continue to receive write data up to 16 bytes. if the a0 to a3 address bits reaches the last ad d r ess o f th e p a g e , th e a0 to a3 ad d r ess b its w ill ro ll o v e r to th e first ad d r ess o f th e same p a g e an d previous write data will be overwritten. upon receiving a stop condition, the eeprom stops receiving w r ite d a ta an d en ters in tern ally -timed w r ite cy cle. page write operation de vice address memor y address wr ite data (n+m) wr ite data (n) 2k 10 10 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k ac k r/w wp rej03c0354-0101 rev.1.01 jan. 9, 2009 page 13 of 22
r1ex24002axxs0a write operations (wp =high ) byte write: (write operation during wp =hi gh st at us ) a wri t e operat i on requi res an 8-bi t devi ce address word wi t h r / w = ?0?. then t h e eepr o m sends acknowledgment "0" at the ninth clock cycle. afte r these, the 2k bit eeprom receives 8-bit memory address. upon receipt of this memory address, the eeprom outputs acknowledgment "0". after receipt of 8-bi t wri t e dat a , t h e eepr o m out put s acknowl e dgment "1" (no ack) . then the eeprom write operat i ons are not al l o wed. byte write operation de vice address memor y address wr ite data (n) 2k 10 10 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k r/w no a c k wp rej03c0354-0101 rev.1.01 jan. 9, 2009 page 14 of 22
r1ex24002axxs0a page wri t e: the page wri t e i s t h e same sequence as t h e byt e wri t e. the page wri t e i s i n i t i a t e d by a st art condi t i on, device address word and memory address(n) with every ninth bit acknowledgmen t"0". but after inputting wri t e dat a (dn) , t h e eepr o m out put s acknowl e dgment "1" (no ack ). then the eeprom write operat i ons are not al l o wed. page write operation de vice address memor y address wr ite data (n+m) wr ite data (n) 2k 10 10 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop star t ac k no a c k ac k r/w wp no a c k rej03c0354-0101 rev.1.01 jan. 9, 2009 page 15 of 22
r1ex24002axxs0a acknowl edge pol l i n g: acknowledge polling feature is used to show if the eep rom is in a inte rnally-timed write cycle or not. thi s feat ure i s i n i t i a t e d by t h e st op condi t i on aft e r i nput t i ng wri t e dat a . thi s requi res t h e 8-bi t devi ce address word fol l o wi ng t h e st art condi t i on duri ng a i n t e rnal l y -t i m ed wri t e cycl e. acknowl e dge pol l i ng wi l l operat e when t h e r / w code = ?0?. acknowl e dgment ?1? (no acknowl e dgment ) shows t h e eepr o m i s i n a i n t e rnal l y -t i m ed wri t e cycl e and acknowl e dgment ?0? shows t h at t h e i n t e rnal l y -t i m ed wri t e cycl e has compl e t e d. see wri t e c y cl e pol l i ng usi ng ac k. write c y cle po lling u s ing a c k send wr ite command send stop condition to initiate wr ite cycle send star t condition send de vice address w ord with r/w = 0 send memor y address send star t condition send stop condition send stop condition proceed r andom address read oper ation proceed wr ite oper ation ne xt oper ation is addressing the memor y ye s ye s no no ac k retur ned rej03c0354-0101 rev.1.01 jan. 9, 2009 page 16 of 22
r1ex24002axxs0a read operati on there are t h ree read operat i ons: current address r ead, random read, and sequent i a l read. r ead operat i ons are initiated the same way as write opera tions with the exception of r/w = ?1?. current address read: the internal address counter mainta ins the last address accessed during th e last read or write operation, with incremented by one. current address read accesses the address kept by the in ternal address counter. after receiving a start condition and the device address word (r/w is ?1?), the eeprom outputs the 8-bit current address dat a from t h e most si gni fi cant bi t fol l o wi ng acknowl e dgment ?0?. if t h e eepr o m receives acknowledgment ?1? (no acknowledgment) a nd a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last address of t h e l a st page at previ ous read operat i on, t h e current a ddress wi l l rol l over and ret u rns t o zero address. in case the eeprom has accessed the last address of the page at previous write opera tion, the current address wi l l rol l over wi t h i n page addressi ng and ret u rns t o t h e fi rst address i n t h e same page. the current address i s val i d whi l e power i s on. the current address aft e r power on wi l l be i ndefi ni t e . the random read operat i on descri bed bel o w i s necessary t o defi ne t h e memory address. current address read operation 2k de vice address read data (n+1) star t stop 10 10 r d7 d6 d5 d4 d3 d2 d1 d0 ac k no a c k r/w rej03c0354-0101 rev.1.01 jan. 9, 2009 page 17 of 22
r1ex24002axxs0a random read: thi s i s a read operat i on wi t h defi ned read address. a random read requi res a dummy wri t e t o set read address. the eeprom receives a start condition, de vice address word (r/w=0) and memory address 8- bit sequentially. the eeprom outputs acknowledgment ?0 ? after receiving memory address then enters a current address read with receivi ng a start condition. the eeprom output s the read data of the address which was defined in the dummy write opera tion. after receiving acknowledgment ?1?(no acknowledgment) and a following stop condition, th e eeprom stops the random read operation and ret u rns t o a st andby st at e. random read operati on @@ @ notes: 1. 2nd de vice address code (#) should be same as 1st (@). de vice address de vice address memor y address read data (n) 2k 10 10 ## # 10 10 r w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t star t ac k no a c k ac k r/w ac k r/w dumm y wr ite current address read rej03c0354-0101 rev.1.01 jan. 9, 2009 page 18 of 22
r1ex24002axxs0a sequential read: sequential reads are initiated by either a current addr ess read or a random read. if the eeprom receives acknowl e dgment ?0? aft e r 8-bi t read dat a , t h e read addre ss i s i n crement e d and t h e next 8-bi t read dat a are coming out. this operation can be continued as long as the eeprom receives acknowledgment ?0?. the address will roll over and returns address zero if it reaches the last address of the last page. the sequent i a l read can be cont i nued aft e r rol l over. the sequent i a l read i s t e rmi n at ed i f t h e eepr o m receives acknowledgment ?1? (no acknowledgm ent) and a following stop condition. sequential read operation de vice address read data (n+m) read data (n+1) read data (n+2) 2k 10 10 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k no a c k ac k r/w ac k rej03c0354-0101 rev.1.01 jan. 9, 2009 page 19 of 22
r1ex24002axxs0a notes data protecti o n at v cc on/off when v cc i s t u rned on or off, noi se on t h e sc l and sda i nput s generat e d by ext e rnal ci rcui t s (c pu, et c) may act as a t r i gger and t u rn t h e eepr o m t o uni nt ent i onal program mode. to prevent t h i s uni nt ent i onal programmi ng, t h i s eepr o m has a power on reset funct i on. b e careful of t h e not i ces descri bed bel o w i n order for t h e power on reset funct i on t o operat e correct l y . ? sc l and sda shoul d be fi xed t o v cc or v ss duri ng v cc on/ off. low t o hi gh or hi gh t o l o w t r ansi t i on duri ng v cc on/ off may cause t h e t r i gger for t h e uni nt ent i onal programmi ng. ? v cc should be turned off after the eep rom is placed in a standby state. ? v cc shoul d be t u rned on from t h e ground l e vel ( v ss ) in order for the eeprom not to enter the uni nt ent i onal programmi ng mode. ? v cc t u rn on speed shoul d be l onger t h an 10 s. noise suppression time thi s eepr o m have a noi se suppressi on funct i on at sc l and sda i nput s, t h at cut noi se of wi dt h l e ss t h an 50 ns. b e careful not t o al l o w noi se of wi dt h more t h an 50 ns. rej03c0354-0101 rev.1.01 jan. 9, 2009 page 20 of 22
r1ex24002axxs0a package dimensions r1e x 24002asas0a (pr sp0008df-b / previ ous c ode: fp-8db v ) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max 5.15 a 1 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-sop8-3.9x4.89-1.27 0.08g mass[typ.] fp-8dbv prsp0008df-b renesas code jeita package code previous code rej03c0354-0101 rev.1.01 jan. 9, 2009 page 21 of 22
r1ex24002axxs0a rej03c0354-0101 rev.1.01 jan. 9, 2009 page 22 of 22 r1e x 24002at a s0a (ptsp0008jc - b / previ ous c ode: ttp-8dav) a l e c 1 b 1 d e a 2 b p c
revision history r1ex24002axxs0a data sheet contents of modification r e v . d a t e p a g e d e s c r i p t i o n 0.01 dec. 26, 2007 ? i n i t i a l i s s u e 1.00 april. 21, 2008 ? deletion of preliminary 1 . 0 1 j a n . 0 9 , 2 0 0 9 p 1 p4 p5 features endurance cycles change 10 6 cycles to 1,000k cycles @ 25 c. data retentions years change 10 years to 100 years @ 25 c. memory cell characteristics new is described. ac characteristics erase/w r ite enduranc e is deleted. notes1. change not 100% tested. notes3 deleted.
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any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire 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sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 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